1. Field of the Invention
The present invention relates to a semiconductor device achieved by adopting an HSG (hemispherical grained silicon) forming technology and a method of manufacturing the semiconductor device.
2. Description of the Related Art
When manufacturing a semiconductor device assuming a multilayer structure such as a DRAM in the prior art, extremely small plugs are formed at inter-layer films in order to electrically connect the layers.
FIGS. 3-5 are cross sectional views illustrating steps taken to form minute plugs at an inter-layer film in the semiconductor device assuming a multilayer structure through a manufacturing method in the prior art.
First, as illustrated in FIG. 3(a), element isolation regions 102, an electrode wiring 103 which may be utilized as, for instance, a bit line and an inter-layer film 104 are formed on a silicon substrate 101 through a method of the known art.
Next, a polysilicon film 105 to constitute a mask is formed over the inter-layer film 104, as shown in FIG. 3(b). It is to be noted that this film may be constituted of amorphous silicon (α-Si).
Then, after forming a film constituted of a resist 106 such as a photoresist on the mask polysilicon film 105, the resist 106 is patterned through lithography to remove the resist 106 over the areas where plugs are to be formed, as illustrated in FIG. 3(c).
When the mask polysilicon film 105 and the interlayer film 104 are etched by using the patterned resist 106 as a mask, as shown in FIG. 3(d) in the following step, areas 107 are formed.
After the remaining resist 106 is removed, a new polysilicon (or α-Si) film is formed. Then, by removing the polysilicon (or α-Si) film through slightly anisotropic etching, polysilicon (or α-Si) sidewalls to be utilized for PSC (poly-sidewall contact), i.e., sidewall polysilicon film 108, formed as illustrated in FIG. 4(a).
As shown in FIG. 4(b), minute contact holes 109 are formed by etching the inter-layer film 104 with the sidewall polysilicon films 108 used as a mask.
Next, a new polysilicon film, i.e., an embedding polysilicon film 110 is formed and part of the embedding polysilicon film 110 enters the contact holes 109 to form plugs in the following step, as illustrated in FIG. 4(c).
Then, as shown in FIG. 4(d), the embedding polysilicon film 110 and the mask polysilicon film 105 are removed through an etch-back or a CMP method (chemical mechanical polishing).
As a result, plugs each having an extremely small lower portion that is joined with the silicon substrate 101, the electrode wiring 103 or the like and a wide upper portion, i.e., a wide receptacle area over which the plug is joined with another layer, are obtained. Thus, as illustrated in FIG. 5, a second layer wiring 112 and a cell contact 113 to be connected with a DRAM capacitor, which are formed in a second inter-layer film 111 above the inter-layer film 104, can be joined with the wide receptacle areas of the plugs even if their positions do not exactly match the positions of the corresponding plugs.
However, in the semiconductor device manufacturing method in the prior art described above in which PSC (poly-sidewall contact) is utilized, the number of film forming steps is bound to be large.
In addition, when etching the mask polysilicon film 105 and the inter-layer film 104 by using the patterned resist 106 as a mask, as illustrated in FIG. 3(d), it is difficult to control the degree to which the inter-layer film 104 is etched.
Furthermore, with a great number of film forming/etching steps implemented, there is a greater risk of an abnormal pattern 114 being formed due to entry of minute impurities, i.e., particles 115. Moreover, since it is more difficult to achieve full control of the degree to which the inter-layer film 104, the second inter-layer film 111 and the like are etched, the receptacle area of a plug may become narrower or the lower end of the cell contact 113 may not reach a specific depth to result in an incomplete junction 115.